Difference between revisions of "Firmware Upgrade"
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(Created page with "== Blocks in file == This is for 2.5 of DS1000E. {| border="1" style="text-align: right; font-family: monospace" !File!!Mem!!Size!!Flags |- |0x1f||0xff800060||0x4||IGNORE |- |0x...") |
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== Blocks in file == | == Blocks in file == | ||
− | This is for 2.5 of DS1000E. | + | This is for 2.5.1.0 of DS1000E. |
+ | |||
+ | * It seems each "module" is separate in the firmware upgrade file, with one ZEROFILL after each code one (if BSS data is needed.) | ||
+ | * The only INIT block contains the same bytes as the one preceding it. | ||
+ | ** It initializes settings for SDRAM. | ||
+ | *** EBIU_SDRRC = 0x0FFF | ||
+ | *** EBIU_SDBCTL = 0x11 (EBE | EBSZ_16MB | EBCAW_9BITS) | ||
+ | *** EBIU_SDGCTL = 0x0091998D | ||
+ | *** EBIU_AMGCTL = 4 (AMBEN_0_1) | ||
+ | * Things up to 0x0100 0000 are in SDRAM. | ||
+ | * 0xFF80 6000 – 0xFF80 8000 are in Data bank A SRAM | ||
+ | * 0xFFA0 8000 and up is Instruction SRAM | ||
{| border="1" style="text-align: right; font-family: monospace" | {| border="1" style="text-align: right; font-family: monospace" | ||
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|0x2d||0xffa08000||0x98||0x0 | |0x2d||0xffa08000||0x98||0x0 | ||
|- | |- | ||
− | |0xcf||0xffa08000||0x2||INIT | + | |0xcf||0xffa08000||0x2||INIT, contains the same data as 0x2d. |
|- | |- | ||
|0xdb||0xff800060||0x4||IGNORE | |0xdb||0xff800060||0x4||IGNORE | ||
Line 15: | Line 26: | ||
|0xe9||0x4||0xfffe||0x0 | |0xe9||0x4||0xfffe||0x0 | ||
|- | |- | ||
− | | | + | |... |
|- | |- | ||
− | | | + | |0xf0161||0xeffe6||0x2b2||0x0 |
|- | |- | ||
− | | | + | |0xf041d||0x19e000||0x192||0x0 |
|- | |- | ||
− | | | + | |0xf05b9||0x608800||0xfffe||0x0 |
|- | |- | ||
− | | | + | |0x1005c1||0x6187fe||0xe920||0x0 |
|- | |- | ||
− | | | + | |0x10eeeb||0x680000||0xfffe||0x0 |
|- | |- | ||
− | | | + | |0x11eef3||0x68fffe||0x4cae||0x0 |
|- | |- | ||
− | | | + | |0x123bab||0x6c0000||0x4||0x0 |
|- | |- | ||
− | | | + | |0x123bb9||0x6c0008||0xd6||0x0 |
|- | |- | ||
− | | | + | |0x123c99||0x6c00de||0x10||ZEROFILL |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | |... |
|- | |- | ||
− | | | + | |0x143175||0xff806000||0xf34||0x1 |
|- | |- | ||
− | | | + | |0x14317f||0xff806f34||0x2||0x0 |
|- | |- | ||
− | | | + | |0x14318b||0xff806f36||0x402||0x1 |
|- | |- | ||
− | | | + | |0x143195||0xff807338||0x2||0x0 |
|- | |- | ||
− | | | + | |0x1431a1||0xff80733a||0x3e4||0x1 |
|- | |- | ||
− | | | + | |0x1431ab||0xff80771e||0x2||0x0 |
|- | |- | ||
− | | | + | |0x1431b7||0xff807720||0x336||0x1 |
|- | |- | ||
− | | | + | |0x1431c1||0xff807a56||0x2||0x0 |
|- | |- | ||
− | | | + | |0x1431cd||0xffa08000||0x156||0x0 |
|- | |- | ||
− | | | + | |0x14332d||0xffa08158||0x6954||FINAL |
|} | |} | ||
+ | |||
+ | |||
+ | == Known Headers and Structure == | ||
+ | |||
+ | |||
+ | |---------------------------------------------------------------------------| | ||
+ | |HEX Address: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14| | ||
+ | |---------------------------------------------------------------------------| | ||
+ | | Fields: |<------ Std. header -------->|<-FW rev.->|<-?->|<- CRC32 ->|??| | ||
+ | |---------------------------------------------------------------------------| | ||
+ | v2.05.01.00: 44 53 31 30 30 30 45 20 20 20 82 85 84 88 C3 7B 47 92 39 C8 7E | ||
+ | v2.05.01.02: 44 53 31 30 30 30 45 20 20 20 82 85 84 82 8B B8 96 41 63 FF 33 | ||
+ | v2.05.02.00: 44 53 31 30 30 30 45 20 20 20 82 85 82 88 C0 7E D7 6A 15 B6 B6 | ||
+ | v2.06.00.01: 4A E3 3E 5E 1C EA 8D 39 9A 23 82 86 88 84 02 8C E9 A6 50 D0 BC |
Latest revision as of 22:37, 1 April 2012
Blocks in file
This is for 2.5.1.0 of DS1000E.
- It seems each "module" is separate in the firmware upgrade file, with one ZEROFILL after each code one (if BSS data is needed.)
- The only INIT block contains the same bytes as the one preceding it.
- It initializes settings for SDRAM.
- EBIU_SDRRC = 0x0FFF
- EBIU_SDBCTL = 0x11 (EBE | EBSZ_16MB | EBCAW_9BITS)
- EBIU_SDGCTL = 0x0091998D
- EBIU_AMGCTL = 4 (AMBEN_0_1)
- It initializes settings for SDRAM.
- Things up to 0x0100 0000 are in SDRAM.
- 0xFF80 6000 – 0xFF80 8000 are in Data bank A SRAM
- 0xFFA0 8000 and up is Instruction SRAM
File | Mem | Size | Flags |
---|---|---|---|
0x1f | 0xff800060 | 0x4 | IGNORE |
0x2d | 0xffa08000 | 0x98 | 0x0 |
0xcf | 0xffa08000 | 0x2 | INIT, contains the same data as 0x2d. |
0xdb | 0xff800060 | 0x4 | IGNORE |
0xe9 | 0x4 | 0xfffe | 0x0 |
... | |||
0xf0161 | 0xeffe6 | 0x2b2 | 0x0 |
0xf041d | 0x19e000 | 0x192 | 0x0 |
0xf05b9 | 0x608800 | 0xfffe | 0x0 |
0x1005c1 | 0x6187fe | 0xe920 | 0x0 |
0x10eeeb | 0x680000 | 0xfffe | 0x0 |
0x11eef3 | 0x68fffe | 0x4cae | 0x0 |
0x123bab | 0x6c0000 | 0x4 | 0x0 |
0x123bb9 | 0x6c0008 | 0xd6 | 0x0 |
0x123c99 | 0x6c00de | 0x10 | ZEROFILL |
... | |||
0x143175 | 0xff806000 | 0xf34 | 0x1 |
0x14317f | 0xff806f34 | 0x2 | 0x0 |
0x14318b | 0xff806f36 | 0x402 | 0x1 |
0x143195 | 0xff807338 | 0x2 | 0x0 |
0x1431a1 | 0xff80733a | 0x3e4 | 0x1 |
0x1431ab | 0xff80771e | 0x2 | 0x0 |
0x1431b7 | 0xff807720 | 0x336 | 0x1 |
0x1431c1 | 0xff807a56 | 0x2 | 0x0 |
0x1431cd | 0xffa08000 | 0x156 | 0x0 |
0x14332d | 0xffa08158 | 0x6954 | FINAL |
Known Headers and Structure
|---------------------------------------------------------------------------| |HEX Address: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14| |---------------------------------------------------------------------------| | Fields: |<------ Std. header -------->|<-FW rev.->|<-?->|<- CRC32 ->|??| |---------------------------------------------------------------------------| v2.05.01.00: 44 53 31 30 30 30 45 20 20 20 82 85 84 88 C3 7B 47 92 39 C8 7E v2.05.01.02: 44 53 31 30 30 30 45 20 20 20 82 85 84 82 8B B8 96 41 63 FF 33 v2.05.02.00: 44 53 31 30 30 30 45 20 20 20 82 85 82 88 C0 7E D7 6A 15 B6 B6 v2.06.00.01: 4A E3 3E 5E 1C EA 8D 39 9A 23 82 86 88 84 02 8C E9 A6 50 D0 BC