Difference between revisions of "General Information"

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(Software)
(Added some hardware infos)
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== Hardware ==
 
== Hardware ==
 
;CPU: [http://www.analog.com/pr/ADSP-BF531 ADSP-BF531]
 
;CPU: [http://www.analog.com/pr/ADSP-BF531 ADSP-BF531]
;Flash EPROM: 4 MB (or is it 8 MB paged by a bootloader?)
+
;Memory:
 +
:Flash EPROM: [http://www.alldatasheet.com/datasheet-pdf/pdf/211252/SPANSION/S29GL064N90TFI040.html S29GL064N90TFI04] - 8MB, 16Bit
 +
:Sample RAM: [http://www.issi.com/pdf/61LPS25632TD.pdf IS61LPS25636A-200] - 256K x 36 200MHz @ 250MHz
 +
:Config FRAM: [http://www.ramtron.com/products/nonvolatile-memory/serial-product.aspx?id=55 FM24CL04B] - 4kb non volatile ferroelectric memory
 +
;A/D Converter
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:10x [http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9288/products/product.html AD9288-40] - 8-Bit, 40MHz MSPS Dual A/D Converter @100MHz
 +
;Programmable Logic:
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:FPGA: Altera Cyclone III EP3C5F256C8N
 +
:CPLD: Lattice Mach XO LCMX0256C-3TN100C
  
 
== Software ==
 
== Software ==

Revision as of 18:11, 5 January 2012

Hardware

CPU
ADSP-BF531
Memory
Flash EPROM: S29GL064N90TFI04 - 8MB, 16Bit
Sample RAM: IS61LPS25636A-200 - 256K x 36 200MHz @ 250MHz
Config FRAM: FM24CL04B - 4kb non volatile ferroelectric memory
A/D Converter
10x AD9288-40 - 8-Bit, 40MHz MSPS Dual A/D Converter @100MHz
Programmable Logic
FPGA: Altera Cyclone III EP3C5F256C8N
CPLD: Lattice Mach XO LCMX0256C-3TN100C

Software

Firmware size
4 MB
Reset vector
0xFFA0 8000
Build with
VirtualDSP 4.x
Operating System
Written from Scratch without a OS(?)