MediaWiki API result
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"8": {
"pageid": 8,
"ns": 0,
"title": "Schematics",
"revisions": [
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"*": "Here you will find some schematics from the Rigol DS1052/DS1102 Hardware Revision 58. The drawings comes from the user [[user:A Helene|A Helene]].\n\n\n== CH1 Analog Frontend ==\n\n[[File:DS1052E_HW58_PCB_Schematics_-_Ch1_analog_front-end.jpg|700px]]\n\n== DAC, Demux, Sample & Hold, Buffers ==\n\n[[File:DS1052E_HW58_PCB_Schematics_-_DAC,_Demux,_Sample_&_Hold,_Buffers.jpg|700px]]\n\n== Keypad PCB ==\n\n[[File:DS1052E HW58 PCB Schematics - Keypad PCB.jpg|700px]]\n\nLED Shift Register connected to SPORT0 from Blackfin\n\n== Trigger input front-end ==\n\n[[File:DS1052E HW58 PCB Schematics - Trigger input front-end.jpg|700px]]\n\n== Trigger, Comparator ==\n\n[[File:DS1052E HW58 PCB Schematics - Trigger, Comparator.jpg|700px]]\n\n== Power Supply Unit ==\n\n[[File:DS1052E PSU schematic.jpg|700px]]\n\n== Asynchronous Memory Bus ==\n\n<pre>\n--------------------------------------------------------------------------------------\n| - Asynchronous Memory bus: |\n|------------------------------------------------------------------------------------|\n| Blackfin | CPLD | FPGA | LA | FLASH |ISP1362 |\n|-----------------------------------------+-------+-------+--------+--------+--------|\n|BF.162: ARDY [I] Ready control (N/C) | | | | | |\n|BF.154: /AOE [O] Output Enable | | | LH1.07 | FLR.28 | |\n|BF.153: /ARE [O] Read Enable | LT.85 | FP.E1 | LH1.10 | | |\n|BF.152: /AWE [O] Write Enable | LT.86 | FP.E2 | LH1.09 | | |\n|BF.161: /AMS0 [O] Bank Select 0 | LT.82 | | | | |\n|BF.160: /AMS1 [O] Bank Select 1 | LT.81 | | | | |\n|BF.159: /AMS2 [O] Bank Select 2 | LT.80 | FP.L8 | | | |\n|BF.158: /AMS3 [O] Bank Select 3 | LT.79 | | | | |\n|BF.051: PF0/SS0 [?] ? (Pulled high) | | | | | |\n|BF.050: PF1/SS1 [I] LA Ready (?) | | | LH1.06 | | |\n|BF.049: PF2/SS2 [I] USB INT1 output | | | | | USB.30 |\n|BF.034: PF10 [I] USB INT2 output | | | | | USB.31 |\n|BF.149: AADDR0 [O] USB A0: Command/Data | | | | | USB.61 |\n|BF.148: AADDR1 [O] USB A1: Device/Host | | | | | USB.62 |\n| N/C [-] USB /RD input | LT.99 | | | | USB.20 |\n| N/C [-] USB /CS input | LT.100| | | | USB.21 |\n| N/C [-] USB /WR input | LT.01 | | | | USB.22 |\n| N/C [-] LA ? | LT.83 | | LH1.08 | | |\n| N/C [-] LA ? | | FP.F6 | LH1.24 | | |\n| N/C [-] FLASH /WP | LT.91 | | | FLR.14 | |\n| N/C [-] FLASH /CE | LT.98 | | | FLR.26 | |\n| N/C [-] FLASH /WE | LT.97 | | | FLR.11 | |\n| N/C [-] FLASH ADDR19 | LT.96 | | | FLR.09 | |\n| N/C [-] FLASH ADDR20 | LT.95 | | | FLR.10 | |\n| N/C [-] FLASH ADDR21 | LT.94 | | | FLR.13 | |\n--------------------------------------------------------------------------------------\n</pre>\n\nBF.x are the pins of BlackFin, [x] is the BlackFin pins direction, LT.x are the pins of the LaTtice CPLD, FP.x the pins of the Altera FPga, LH1.x those of the Logic Analyser Header 1 (the 40 pins one), FLR.x those of the Spansion FLash Ram and USB.x the pins of the Philips ISP1362 USB On-The-Go controller. All the components above share the same 16-bits data bus and the 21-bit Address bus; the BlackFin address bus is 19-bits wide, the address bus width of the CPLD, the FPGA and the Logic Analyser is 8-bits and the USB chip is controlled by the two lower address bus lines.\n\n\n== Programming connector ==\n\nLooks like the default Blackfin Connector. Tests are outstanding."
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"19": {
"pageid": 19,
"ns": 0,
"title": "Start Development",
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"*": "Sorry, not complete yet, you will find some starting point in the examples delivered with the toolchain...\n\n\n\n\n\n----\n\n=== Todo ===\n\nhowto compile examples\n\n\n\n-----------------\n=== Blackfin programming reference ===\n: If you are new to blackfin development it may be a good idea to read this document.\n: [http://www.analog.com/static/imported-files/processor_manuals/bf533_hwr_Rev3.4.pdf Blackfin Processor Hardware Reference]\n\n=== Pitfalls ===\n\n; Alignment\n: Every command must be word aligned. When you access the memory, word accesses must be word aligned, long word accesses must be long word aligned. \n: '''Don't''' use the .align directive . It doesn't works with the toolchain. Use .byte directives to do that.\n\n; Subroutines / Calls\n: Every subroutine that calls subroutines must start with LINK and end with UNLINK to save the return address to the stack. The blackfin CPU doesn't do that automaticly.\n\nExample:\n<pre>\nsub:\n LINK 0x0\n\n ...\n CALL sub2\n ...\n\n UNLINK\n RTS\n</pre>\n\n; STOP-Mode\n: Switch your scope to the STOP-Mode if you don't need capturing during your software is working. Sometimes i got unpredictable crashs when the device was in AUTO-Mode. Hope to find a reason for this thing soon.\n\n=== Unlock the Keyboard ===\n: If you need keyboard interaction, first you should unlock the keyboard for user inputs.\n: This lines will do the job:\n<pre>\n R0=0\n CALL Set_KeyLock\n</pre>\n: The keyboard is locked, because the serial interface is used to upload and start your software.\n: You can see that its locked if the only keycode you get is KC_KEYLOCK (0xc9)."
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