Rigol Homebrew Wiki - User contributions [en]

Start Development

2013-04-25T13:33:07Z

Matt:

Sorry, not complete yet, you will find some starting point in the examples delivered with the toolchain...

----

=== Todo ===

howto compile examples

-----------------
=== Blackfin programming reference ===
: If you are new to blackfin development it may be a good idea to read this document.
: [http://www.analog.com/static/imported-files/processor_manuals/bf533_hwr_Rev3.4.pdf Blackfin Processor Hardware Reference]

=== Pitfalls ===

; Alignment
: Every command must be word aligned. When you access the memory, word accesses must be word aligned, long word accesses must be long word aligned.
: '''Don't''' use the .align directive . It doesn't works with the toolchain. Use .byte directives to do that.

; Subroutines / Calls
: Every subroutine that calls subroutines must start with LINK and end with UNLINK to save the return address to the stack. The blackfin CPU doesn't do that automaticly.

Example:
<pre>
sub:
LINK 0x0

...
CALL sub2
...

UNLINK
RTS
</pre>

; STOP-Mode
: Switch your scope to the STOP-Mode if you don't need capturing during your software is working. Sometimes i got unpredictable crashs when the device was in AUTO-Mode. Hope to find a reason for this thing soon.

=== Unlock the Keyboard ===
: If you need keyboard interaction, first you should unlock the keyboard for user inputs.
: This lines will do the job:
<pre>
R0=0
CALL Set_KeyLock
</pre>
: The keyboard is locked, because the serial interface is used to upload and start your software.
: You can see that its locked if the only keycode you get is KC_KEYLOCK (0xc9).

Start Development

2013-04-25T13:31:40Z

Matt:

Sorry, not complete yet, you will find some starting point in the examples delivered with the toolchain...

----

=== Todo ===

howto compile examples

-----------------
=== Blackfin programming reference ===
If you are new to blackfin development it may be a good idea to read this document.
* [http://www.analog.com/static/imported-files/processor_manuals/bf533_hwr_Rev3.4.pdf Blackfin Processor Hardware Reference]

=== Pitfalls ===

; Alignment
: Every command must be word aligned. When you access the memory, word accesses must be word aligned, long word accesses must be long word aligned.
: '''Don't''' use the .align directive . It doesn't works with the toolchain. Use .byte directives to do that.

; Subroutines / Calls
: Every subroutine that calls subroutines must start with LINK and end with UNLINK to save the return address to the stack. The blackfin CPU doesn't do that automaticly.

Example:
<pre>
sub:
LINK 0x0

...
CALL sub2
...

UNLINK
RTS
</pre>

; STOP-Mode
: Switch your scope to the STOP-Mode if you don't need capturing during your software is working. Sometimes i got unpredictable crashs when the device was in AUTO-Mode. Hope to find a reason for this thing soon.

=== Unlock the Keyboard ===
: If you need keyboard interaction, first you should unlock the keyboard for user inputs.
: This lines will do the job:
<pre>
R0=0
CALL Set_KeyLock
</pre>
: The keyboard is locked, because the serial interface is used to upload and start your software.
: You can see that its locked if the only keycode you get is KC_KEYLOCK (0xc9).

Start Development

2013-04-25T13:30:00Z

Matt:

Sorry, not complete yet, you will find some starting point in the examples delivered with the toolchain...

----

=== Todo ===

howto compile examples

-----------------
=== Blackfin programming reference ===
If you are new to blackfin development it may be a good idea to read this document.
* [http://www.analog.com/static/imported-files/processor_manuals/bf533_hwr_Rev3.4.pdf Blackfin Processor Hardware Reference]

=== Pitfalls ===

; Alignment
: Every command must be word aligned. When you access the memory, word accesses must be word aligned, long word accesses must be long word aligned.
: '''Don't''' use the .align directive . It doesn't works with the toolchain. Use .byte directives to do that.

; Subroutines / Calls
: Every subroutine that calls subroutines must start with LINK and end with UNLINK to save the return address to the stack. The blackfin CPU doesn't do that automaticly.

Example:
<pre>
sub:
LINK 0x0

...
CALL sub2
...

UNLINK
RTS
</pre>

; STOP-Mode
: Switch your scope to the STOP-Mode if you don't need capturing during your software is working. Sometimes i got unpredictable crashs when the device was in AUTO-Mode. Hope to find a reason for this thing soon.

; Unlock the Keyboard
: If you need keyboard interaction, first you should unlock the keyboard for user inputs.
: This lines will do the job:
<pre>
R0=0
CALL Set_KeyLock
</pre>
: The keyboard is locked, because the serial interface is used to upload and start your software.
: You can see that its locked if the only keycode you get is KC_KEYLOCK (0xc9).

Schematics

2012-11-20T11:52:17Z

Matt:

Here you will find some schematics from the Rigol DS1052/DS1102 Hardware Revision 58. The drawings comes from the user [[user:A Helene|A Helene]].

== CH1 Analog Frontend ==

[[File:DS1052E_HW58_PCB_Schematics_-_Ch1_analog_front-end.jpg|700px]]

== DAC, Demux, Sample & Hold, Buffers ==

[[File:DS1052E_HW58_PCB_Schematics_-_DAC,_Demux,_Sample_&_Hold,_Buffers.jpg|700px]]

== Keypad PCB ==

[[File:DS1052E HW58 PCB Schematics - Keypad PCB.jpg|700px]]

== Trigger input front-end ==

[[File:DS1052E HW58 PCB Schematics - Trigger input front-end.jpg|700px]]

== Trigger, Comparator ==

[[File:DS1052E HW58 PCB Schematics - Trigger, Comparator.jpg|700px]]

== Power Supply Unit ==

[[File:DS1052E PSU schematic.jpg|700px]]

== Asynchronous Memory Bus ==

<pre>
--------------------------------------------------------------------------------------
| - Asynchronous Memory bus: |
|------------------------------------------------------------------------------------|
| Blackfin | CPLD | FPGA | LA | FLASH |ISP1362 |
|-----------------------------------------+-------+-------+--------+--------+--------|
|BF.162: ARDY [I] Ready control (N/C) | | | | | |
|BF.154: /AOE [O] Output Enable | | | LH1.07 | FLR.28 | |
|BF.153: /ARE [O] Read Enable | LT.85 | FP.E1 | LH1.10 | | |
|BF.152: /AWE [O] Write Enable | LT.86 | FP.E2 | LH1.09 | | |
|BF.161: /AMS0 [O] Bank Select 0 | LT.82 | | | | |
|BF.160: /AMS1 [O] Bank Select 1 | LT.81 | | | | |
|BF.159: /AMS2 [O] Bank Select 2 | LT.80 | FP.L8 | | | |
|BF.158: /AMS3 [O] Bank Select 3 | LT.79 | | | | |
|BF.051: PF0/SS0 [?] ? (Pulled high) | | | | | |
|BF.050: PF1/SS1 [I] LA Ready (?) | | | LH1.06 | | |
|BF.049: PF2/SS2 [I] USB INT1 output | | | | | USB.30 |
|BF.034: PF10 [I] USB INT2 output | | | | | USB.31 |
|BF.149: AADDR0 [O] USB A0: Command/Data | | | | | USB.61 |
|BF.148: AADDR1 [O] USB A1: Device/Host | | | | | USB.62 |
| N/C [-] USB /RD input | LT.99 | | | | USB.20 |
| N/C [-] USB /CS input | LT.100| | | | USB.21 |
| N/C [-] USB /WR input | LT.01 | | | | USB.22 |
| N/C [-] LA ? | LT.83 | | LH1.08 | | |
| N/C [-] LA ? | | FP.F6 | LH1.24 | | |
| N/C [-] FLASH /WP | LT.91 | | | FLR.14 | |
| N/C [-] FLASH /CE | LT.98 | | | FLR.26 | |
| N/C [-] FLASH /WE | LT.97 | | | FLR.11 | |
| N/C [-] FLASH ADDR19 | LT.96 | | | FLR.09 | |
| N/C [-] FLASH ADDR20 | LT.95 | | | FLR.10 | |
| N/C [-] FLASH ADDR21 | LT.94 | | | FLR.13 | |
--------------------------------------------------------------------------------------
</pre>

BF.x are the pins of BlackFin, [x] is the BlackFin pins direction, LT.x are the pins of the LaTtice CPLD, FP.x the pins of the Altera FPga, LH1.x those of the Logic Analyser Header 1 (the 40 pins one), FLR.x those of the Spansion FLash Ram and USB.x the pins of the Philips ISP1362 USB On-The-Go controller. All the components above share the same 16-bits data bus and the 21-bit Address bus; the BlackFin address bus is 19-bits wide, the address bus width of the CPLD, the FPGA and the Logic Analyser is 8-bits and the USB chip is controlled by the two lower address bus lines.

== Programming connector ==

Info about the programming connector next to the usb port is required. Send any info to matt@yarrd.co.uk

- Matt

JTAG

2012-11-20T11:17:59Z

Matt:

== Pinout of the JTAG Header ==

--------
3,3V(10k+3v3) <| o o |> /EMU (83)
| |
| o |> GND
| |
GND <| o o |> CPU Pin85 = TMS
| |
GND <| o o |> CPU Pin94 = TCK (10k)
| |
GND <| o o |> /TRST (84) (10k)
| |
GND <| o o |> CPU Pin86 = TDI (10k)
| |
GND <| o o |> CPU Pin87 = TDO 100-
--------

----
If anyone has managed to get the jtag port to work please email matt(at)yarrd.co.uk with details as it will help the project and my resaerch greatly.

- Matt

Patch your Firmware

2012-06-26T12:33:19Z

Matt:

Before you can start to develop your own software, you need a possibility to upload and start it on your Rigol device. Because the original firmware doesn't offers this possibility, we must patch some things to open the door to the memory.

For this job you need
* The completly installed Blackfin and Rigol toolchain (follow the instructions [[Build_the_Toolchain|here]])
* A installed md5sum tool
* A original Rigol firmware image (DS1000EUpdate.RGL) version 02.05.02.00 with a md5sum of 9c28690d8d5a5690b7340fda943f5549.

The md5sum of the firmware can be verified with the command:

md5sum -b DS1000EUpdate.RGL

There is a patch script in the examples/rwpatch/ subdirectory of the toolchain.
Copy your firmware image to <toolchain>/examples/rwpatch/DS1000EUpdate.RGL (where <toolchain> is the path where you installed the rigol toolchain), switch to this directory and do a

<pre>
make patch
</pre>

When all is working correct you get the response:

<pre>
...
</pre>

The resulting firmware should have the md5sum '''3ffccd4edcc70710e010124edec9ee1c'''.
Now you can copy the new firmware image to a usb stick and flash it to your oscilloscope. 


{{warning|'''ATTENTION !!!'''
This will possibly void your warranty or damage your oscilloscope.
Make sure your device will work with version 02.05.02.00 of the original firmware BEFORE you flash the image. We are not responsible for any damage happens while you using this software.}}
 

=== Enjoy the new possibilities ===

After the patch the :FFT command of your serial console will no longer work as usual, but you have some new functions:

;Read bytes from any memory address:
<pre>
:FFT:xxxxxxxxRcc<return>

xxxxxxxx: 8 digit hex address
cc: 2 digit count of bytes to read
</pre>

;Write a byte to memory:
<pre>
:FFT:xxxxxxxWvv<return>

xxxxxxxx: 8 digit hex address
vv: 2 digit value for the byte
</pre>

;Call a subroutine:
<pre>
:FFT:xxxxxxxxCdd<return>

xxxxxxxx: 8 digit hex address
dd: 2 digit dummy
</pre>

 

{{warning|'''ATTENTION !!!'''
Only use this commands if you really know what you do ! It could delete your calibration infos and firmware. We are not responsible for things you do.}}
 

Next step:[[Start_Development]]

Build the Toolchain

2012-06-26T12:20:36Z

Matt:

== Download and install the Rigol toolchain ==

Install git if needed:

sudo apt-get install git

To get the latest version of the toolchain, simply checkout the appropriate git repository with the line:

git clone git://github.com/krater/rigol-toolchain.git

Switch to the resulting directory:

cd rigol-toolchain

Execute the install script, this will install all required packages and install the tool chain on your system:

./install.sh

 Now you are prepared for [[Patch_your_Firmware|patching your firmware]] and building the examples.

Next step: [[Patch_your_Firmware]]

Build the Toolchain

2012-06-26T12:05:11Z

Matt:

== Download and install the Rigol toolchain ==

To get the latest version of the toolchain, simply checkout the appropriate git repository with the line:

git clone git://github.com/krater/rigol-toolchain.git

Switch to the resulting directory and start a make with

cd rigol-toolchain

Execute the install script, this will install all required packages and install the tool chain on your system.

./install.sh

 Now you are prepared for [[Patch_your_Firmware|patching your firmware]] and building the examples.

Next step: [[Patch_your_Firmware]]

Main Page

2012-06-21T17:19:39Z

Matt:

{{:Main Page/Welcome}}

{{col-begin}}
{{col-2}}
{{HeadingA|Toolchain}}
====Getting started====
* [[Build the Toolchain]]
* [[Patch your Firmware]]
* [[Start Development]]

{{col-2}}
{{HeadingB|Reverse Engineering}}
====General Information====
*[[General Information/Software|Software]]
*[[General Information/Hardware|Hardware]]

====Software====
* [[Mapfile]]
* [[Flirt Signatures]]
* [[Firmware Upgrade]]

====Hardware====
* [[JTAG]]
* [[Schematics]]
* [[Hardware/Pictures]]
* [[Hardware/References]]

{{col-end}}

{{col-begin}}
{{col-2}}
{{HeadingA|Applications & Guides}}

====Applications====
====Tutorials====
====Ideas====
* [[Waterfall Plot for FFT]]
* [[Protocol Analyzer]]
* [[Software Defined Radio]]
* [[u-boot]]
* [[linux]]

{{col-2}}
{{HeadingB|Developers & Writers}}

* [[User:krater|krater (Andreas Schuler)]]
* [[user:A Helene|A Helene]]
* [[user:matt|Matt (Matthew Ellis)]]

{{col-end}}

{| border="1" class="wikitable" style="background-color:orange; width:100%;"
|-
|colspan="4" style="background-color:orange; text-align:center;"| [[Disclaimer]]
|}

__NOTOC____NOEDITSECTION__

General Information/Hardware

2012-01-09T09:09:23Z

Matt:

;CPU: [http://www.analog.com/pr/ADSP-BF531 ADSP-BF531]
;Memory:
:Flash EPROM: [http://www.alldatasheet.com/datasheet-pdf/pdf/211252/SPANSION/S29GL064N90TFI040.html S29GL064N90TFI04] - 8MB, 16Bit, DS1052E dump[http://www.eevblog.com/forum/index.php?action=dlattach;topic=30.0;attach=1920]
:Sample RAM: [http://www.issi.com/pdf/61LPS25632TD.pdf IS61LPS25636A-200] - 256kx36, 200MHz @ 250MHz
:Config FRAM: [http://www.ramtron.com/products/nonvolatile-memory/serial-product.aspx?id=55 FM24CL04B] - 4kb non volatile ferroelectric memory, DS1052E dumps[http://www.eevblog.com/forum/index.php?topic=30.msg2783#msg2783][http://www.eevblog.com/forum/index.php?topic=30.msg2788#msg2788]
:SDRAM: [http://www.hynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/consumer/H57V1262GTR_Series(Rev.1.0).pdf H57V1262GTR] - 4x2x16 Mb (16 MB)
;A/D Converter
:5x [http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9288/products/product.html AD9288-40] - 8-Bit, 40MHz MSPS Dual A/D Converter @100MHz
;A/D Driver: [http://www.national.com/ds/LM/LMH6552.pdf LMH6552] or [http://www.national.com/ds/LM/LMH6552.pdf LMH6553][http://www.eevblog.com/forum/index.php?topic=30.msg2107#msg2107]?
;A/D references: [http://www.eevblog.com/forum/index.php?topic=30.msg22457#msg22457 Multiplexed DAC]
;Programmable Logic:
:FPGA: Altera Cyclone III [http://datasheet.octopart.com/EP3C5F256C8N-Altera-datasheet-6401537.pdf EP3C5F256C8N]
::Logic blocks:321
::Family type:cyclone iii
::Total ram bits:423936
::I/O's:182
::Core supply voltage range:1.15v to 1.25v
::I/O supply voltage:3.3v
::Operating frequency max:402mhz
::Package style:bga
::Pins:256
::Supply voltage range :2.375v to 2.625v

:CPLD: Lattice Mach XO [http://datasheet.octopart.com/LCMXO256C-3TN100C-Lattice-Semiconductor-datasheet-166530.pdf LCMXO256C-3TN100C]
::I/O lines:78
::Macrocells:128
::frequency:500mhz
::voltage, supply range 1.71v to 3.465v
::Package style:tqfp
::Pins:100

;Logic analyzer driver: National Semi DS90LV047A[http://www.rcgroups.com/forums/showpost.php?p=11714369&postcount=385][http://www.rcgroups.com/forums/showpost.php?p=11714861&postcount=386][http://www.rcgroups.com/forums/showpost.php?p=11717320&postcount=390]
;USB interface: [http://www.cs.columbia.edu/~sedwards/classes/2010/4840/Philips-ISP1362-USB-controller.pdf ISP1362BD][http://www.eevblog.com/forum/index.php?topic=3738.msg50242#msg50242]
;LCD controller: [http://pdf.chinaicmart.com/88888/200842210717180.pdf UPS051][http://www.eevblog.com/forum/index.php?topic=3738.msg50503#msg50503] or Himax HX8802-C [http://img683.imageshack.us/img683/6131/rigolds1102e.jpg]

General Information

2012-01-08T21:31:54Z

Matt:

== Hardware ==
;CPU: [http://www.analog.com/pr/ADSP-BF531 ADSP-BF531]
;Memory:
:Flash EPROM: [http://www.alldatasheet.com/datasheet-pdf/pdf/211252/SPANSION/S29GL064N90TFI040.html S29GL064N90TFI04] - 8MB, 16Bit, DS1052E dump[http://www.eevblog.com/forum/index.php?action=dlattach;topic=30.0;attach=1920]
:Sample RAM: [http://www.issi.com/pdf/61LPS25632TD.pdf IS61LPS25636A-200] - 256kx36, 200MHz @ 250MHz
:Config FRAM: [http://www.ramtron.com/products/nonvolatile-memory/serial-product.aspx?id=55 FM24CL04B] - 4kb non volatile ferroelectric memory, DS1052E dumps[http://www.eevblog.com/forum/index.php?topic=30.msg2783#msg2783][http://www.eevblog.com/forum/index.php?topic=30.msg2788#msg2788]
:SDRAM: [http://www.hynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/consumer/H57V1262GTR_Series(Rev.1.0).pdf H57V1262GTR] - 4x2x16 Mb (16 MB)
;A/D Converter
:5x [http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9288/products/product.html AD9288-40] - 8-Bit, 40MHz MSPS Dual A/D Converter @100MHz
;A/D Driver: [http://www.national.com/ds/LM/LMH6552.pdf LMH6552] or [http://www.national.com/ds/LM/LMH6552.pdf LMH6553][http://www.eevblog.com/forum/index.php?topic=30.msg2107#msg2107]?
;A/D references: [http://www.eevblog.com/forum/index.php?topic=30.msg22457#msg22457 Multiplexed DAC]
;Programmable Logic:
:FPGA: Altera Cyclone III [http://datasheet.octopart.com/EP3C5F256C8N-Altera-datasheet-6401537.pdf EP3C5F256C8N]
::Logic blocks:321
::Family type:cyclone iii
::Total ram bits:423936
::I/O's:182
::Core supply voltage range:1.15v to 1.25v
::I/O supply voltage:3.3v
::Operating frequency max:402mhz
::Case style:bga
::No. of pins:256
::Supply voltage range :2.375v to 2.625v

:CPLD: Lattice Mach XO [http://datasheet.octopart.com/LCMXO256C-3TN100C-Lattice-Semiconductor-datasheet-166530.pdf LCMXO256C-3TN100C]
::no of i/o lines:78
::no. of macrocells:128
::frequency:500mhz
::voltage, supply range 1.71v to 3.465v
::case style:tqfp
::no. of pins:100

;Logic analyzer driver: National Semi DS90LV047A[http://www.rcgroups.com/forums/showpost.php?p=11714369&postcount=385][http://www.rcgroups.com/forums/showpost.php?p=11714861&postcount=386][http://www.rcgroups.com/forums/showpost.php?p=11717320&postcount=390]
;USB interface: [http://www.cs.columbia.edu/~sedwards/classes/2010/4840/Philips-ISP1362-USB-controller.pdf ISP1362BD][http://www.eevblog.com/forum/index.php?topic=3738.msg50242#msg50242]
;LCD controller: [http://pdf.chinaicmart.com/88888/200842210717180.pdf UPS051][http://www.eevblog.com/forum/index.php?topic=3738.msg50503#msg50503] or Himax HX8802-C [http://img683.imageshack.us/img683/6131/rigolds1102e.jpg]

== Software ==
;Firmware size: 4 MB
;Reset vector: 0xFFA0 8000
;Build with: VirtualDSP 4.x
;Operating System: Written from scratch without a OS(?)

=== Boot loader ===
* [http://www.eevblog.com/forum/index.php?topic=30.msg3160#msg3160 SPI secondary boot loader]

=== Command interface ===
* [http://www.rcgroups.com/forums/showpost.php?p=13549739&postcount=727 Some undocumented 488 commands of DS1000E 2.2.2]
* [http://www.rcgroups.com/forums/showpost.php?p=15479444&postcount=912 Some 2.4.0.3 undocumented 488 commands]
* [http://www.rigolna.com/pdfs/Programming_Guides/DS1000E_Programming_Guide.pdf DS1000E Programming Guide]

General Information

2012-01-08T21:26:31Z

Matt:

== Hardware ==
;CPU: [http://www.analog.com/pr/ADSP-BF531 ADSP-BF531]
;Memory:
:Flash EPROM: [http://www.alldatasheet.com/datasheet-pdf/pdf/211252/SPANSION/S29GL064N90TFI040.html S29GL064N90TFI04] - 8MB, 16Bit, DS1052E dump[http://www.eevblog.com/forum/index.php?action=dlattach;topic=30.0;attach=1920]
:Sample RAM: [http://www.issi.com/pdf/61LPS25632TD.pdf IS61LPS25636A-200] - 256kx36, 200MHz @ 250MHz
:Config FRAM: [http://www.ramtron.com/products/nonvolatile-memory/serial-product.aspx?id=55 FM24CL04B] - 4kb non volatile ferroelectric memory, DS1052E dumps[http://www.eevblog.com/forum/index.php?topic=30.msg2783#msg2783][http://www.eevblog.com/forum/index.php?topic=30.msg2788#msg2788]
:SDRAM: [http://www.hynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/consumer/H57V1262GTR_Series(Rev.1.0).pdf H57V1262GTR] - 4x2x16 Mb (16 MB)
;A/D Converter
:5x [http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9288/products/product.html AD9288-40] - 8-Bit, 40MHz MSPS Dual A/D Converter @100MHz
;A/D Driver: [http://www.national.com/ds/LM/LMH6552.pdf LMH6552] or [http://www.national.com/ds/LM/LMH6552.pdf LMH6553][http://www.eevblog.com/forum/index.php?topic=30.msg2107#msg2107]?
;A/D references: [http://www.eevblog.com/forum/index.php?topic=30.msg22457#msg22457 Multiplexed DAC]
;Programmable Logic:
:FPGA: Altera Cyclone III [http://datasheet.octopart.com/EP3C5F256C8N-Altera-datasheet-6401537.pdf EP3C5F256C8N]
::Logic blocks:321
::Family type:cyclone iii
::Total ram bits:423936
::I/O's:182
::Core supply voltage range:1.15v to 1.25v
::I/O supply voltage:3.3v
::Operating frequency max:402mhz
::Case style:bga
::No. of pins:256
::Supply voltage range :2.375v to 2.625v

:CPLD: Lattice Mach XO [http://datasheet.octopart.com/LCMXO256C-3TN100C-Lattice-Semiconductor-datasheet-166530.pdf LCMXO256C-3TN100C]
;Logic analyzer driver: National Semi DS90LV047A[http://www.rcgroups.com/forums/showpost.php?p=11714369&postcount=385][http://www.rcgroups.com/forums/showpost.php?p=11714861&postcount=386][http://www.rcgroups.com/forums/showpost.php?p=11717320&postcount=390]
;USB interface: [http://www.cs.columbia.edu/~sedwards/classes/2010/4840/Philips-ISP1362-USB-controller.pdf ISP1362BD][http://www.eevblog.com/forum/index.php?topic=3738.msg50242#msg50242]
;LCD controller: [http://pdf.chinaicmart.com/88888/200842210717180.pdf UPS051][http://www.eevblog.com/forum/index.php?topic=3738.msg50503#msg50503] or Himax HX8802-C [http://img683.imageshack.us/img683/6131/rigolds1102e.jpg]

== Software ==
;Firmware size: 4 MB
;Reset vector: 0xFFA0 8000
;Build with: VirtualDSP 4.x
;Operating System: Written from scratch without a OS(?)

=== Boot loader ===
* [http://www.eevblog.com/forum/index.php?topic=30.msg3160#msg3160 SPI secondary boot loader]

=== Command interface ===
* [http://www.rcgroups.com/forums/showpost.php?p=13549739&postcount=727 Some undocumented 488 commands of DS1000E 2.2.2]
* [http://www.rcgroups.com/forums/showpost.php?p=15479444&postcount=912 Some 2.4.0.3 undocumented 488 commands]
* [http://www.rigolna.com/pdfs/Programming_Guides/DS1000E_Programming_Guide.pdf DS1000E Programming Guide]

General Information

2012-01-08T21:24:14Z

Matt:

== Hardware ==
;CPU: [http://www.analog.com/pr/ADSP-BF531 ADSP-BF531]
;Memory:
:Flash EPROM: [http://www.alldatasheet.com/datasheet-pdf/pdf/211252/SPANSION/S29GL064N90TFI040.html S29GL064N90TFI04] - 8MB, 16Bit, DS1052E dump[http://www.eevblog.com/forum/index.php?action=dlattach;topic=30.0;attach=1920]
:Sample RAM: [http://www.issi.com/pdf/61LPS25632TD.pdf IS61LPS25636A-200] - 256kx36, 200MHz @ 250MHz
:Config FRAM: [http://www.ramtron.com/products/nonvolatile-memory/serial-product.aspx?id=55 FM24CL04B] - 4kb non volatile ferroelectric memory, DS1052E dumps[http://www.eevblog.com/forum/index.php?topic=30.msg2783#msg2783][http://www.eevblog.com/forum/index.php?topic=30.msg2788#msg2788]
:SDRAM: [http://www.hynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/consumer/H57V1262GTR_Series(Rev.1.0).pdf H57V1262GTR] - 4x2x16 Mb (16 MB)
;A/D Converter
:5x [http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9288/products/product.html AD9288-40] - 8-Bit, 40MHz MSPS Dual A/D Converter @100MHz
;A/D Driver: [http://www.national.com/ds/LM/LMH6552.pdf LMH6552] or [http://www.national.com/ds/LM/LMH6552.pdf LMH6553][http://www.eevblog.com/forum/index.php?topic=30.msg2107#msg2107]?
;A/D references: [http://www.eevblog.com/forum/index.php?topic=30.msg22457#msg22457 Multiplexed DAC]
;Programmable Logic:
:FPGA: Altera Cyclone III [http://datasheet.octopart.com/EP3C5F256C8N-Altera-datasheet-6401537.pdf EP3C5F256C8N]
::Logic blocks:321
::Family type:cyclone iii
::Total ram bits:423936
::I/O's:182
::Core supply voltage range:1.15v to 1.25v
::I/O supply voltage:3.3v
::Operating frequency max:402mhz
::Case style:bga
::No. of pins:256
::Supply voltage range :2.375v to 2.625v

:CPLD: Lattice Mach XO LCMXO256C-3TN100C
;Logic analyzer driver: National Semi DS90LV047A[http://www.rcgroups.com/forums/showpost.php?p=11714369&postcount=385][http://www.rcgroups.com/forums/showpost.php?p=11714861&postcount=386][http://www.rcgroups.com/forums/showpost.php?p=11717320&postcount=390]
;USB interface: [http://www.cs.columbia.edu/~sedwards/classes/2010/4840/Philips-ISP1362-USB-controller.pdf ISP1362BD][http://www.eevblog.com/forum/index.php?topic=3738.msg50242#msg50242]
;LCD controller: [http://pdf.chinaicmart.com/88888/200842210717180.pdf UPS051][http://www.eevblog.com/forum/index.php?topic=3738.msg50503#msg50503] or Himax HX8802-C [http://img683.imageshack.us/img683/6131/rigolds1102e.jpg]

== Software ==
;Firmware size: 4 MB
;Reset vector: 0xFFA0 8000
;Build with: VirtualDSP 4.x
;Operating System: Written from scratch without a OS(?)

=== Boot loader ===
* [http://www.eevblog.com/forum/index.php?topic=30.msg3160#msg3160 SPI secondary boot loader]

=== Command interface ===
* [http://www.rcgroups.com/forums/showpost.php?p=13549739&postcount=727 Some undocumented 488 commands of DS1000E 2.2.2]
* [http://www.rcgroups.com/forums/showpost.php?p=15479444&postcount=912 Some 2.4.0.3 undocumented 488 commands]
* [http://www.rigolna.com/pdfs/Programming_Guides/DS1000E_Programming_Guide.pdf DS1000E Programming Guide]

General Information

2012-01-08T21:22:25Z

Matt:

== Hardware ==
;CPU: [http://www.analog.com/pr/ADSP-BF531 ADSP-BF531]
;Memory:
:Flash EPROM: [http://www.alldatasheet.com/datasheet-pdf/pdf/211252/SPANSION/S29GL064N90TFI040.html S29GL064N90TFI04] - 8MB, 16Bit, DS1052E dump[http://www.eevblog.com/forum/index.php?action=dlattach;topic=30.0;attach=1920]
:Sample RAM: [http://www.issi.com/pdf/61LPS25632TD.pdf IS61LPS25636A-200] - 256kx36, 200MHz @ 250MHz
:Config FRAM: [http://www.ramtron.com/products/nonvolatile-memory/serial-product.aspx?id=55 FM24CL04B] - 4kb non volatile ferroelectric memory, DS1052E dumps[http://www.eevblog.com/forum/index.php?topic=30.msg2783#msg2783][http://www.eevblog.com/forum/index.php?topic=30.msg2788#msg2788]
:SDRAM: [http://www.hynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/consumer/H57V1262GTR_Series(Rev.1.0).pdf H57V1262GTR] - 4x2x16 Mb (16 MB)
;A/D Converter
:5x [http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9288/products/product.html AD9288-40] - 8-Bit, 40MHz MSPS Dual A/D Converter @100MHz
;A/D Driver: [http://www.national.com/ds/LM/LMH6552.pdf LMH6552] or [http://www.national.com/ds/LM/LMH6552.pdf LMH6553][http://www.eevblog.com/forum/index.php?topic=30.msg2107#msg2107]?
;A/D references: [http://www.eevblog.com/forum/index.php?topic=30.msg22457#msg22457 Multiplexed DAC]
;Programmable Logic:
:FPGA: Altera Cyclone III [http://datasheet.octopart.com/EP3C5F256C8N-Altera-datasheet-6401537.pdf EP3C5F256C8N]
::Logic blocks:321
::Family type:cyclone iii
::Total ram bits:423936
::I/O's:182
::Core supply voltage range:1.15v to 1.25v
::I/O supply voltage:3.3v
::Operating frequency max:402mhz
::Case style:bga
::No. of pins:256
::Supply voltage range :2.375v to 2.625v

:CPLD: Lattice Mach XO LCMX0256C-3TN100C
;Logic analyzer driver: National Semi DS90LV047A[http://www.rcgroups.com/forums/showpost.php?p=11714369&postcount=385][http://www.rcgroups.com/forums/showpost.php?p=11714861&postcount=386][http://www.rcgroups.com/forums/showpost.php?p=11717320&postcount=390]
;USB interface: [http://www.cs.columbia.edu/~sedwards/classes/2010/4840/Philips-ISP1362-USB-controller.pdf ISP1362BD][http://www.eevblog.com/forum/index.php?topic=3738.msg50242#msg50242]
;LCD controller: [http://pdf.chinaicmart.com/88888/200842210717180.pdf UPS051][http://www.eevblog.com/forum/index.php?topic=3738.msg50503#msg50503] or Himax HX8802-C [http://img683.imageshack.us/img683/6131/rigolds1102e.jpg]

== Software ==
;Firmware size: 4 MB
;Reset vector: 0xFFA0 8000
;Build with: VirtualDSP 4.x
;Operating System: Written from scratch without a OS(?)

=== Boot loader ===
* [http://www.eevblog.com/forum/index.php?topic=30.msg3160#msg3160 SPI secondary boot loader]

=== Command interface ===
* [http://www.rcgroups.com/forums/showpost.php?p=13549739&postcount=727 Some undocumented 488 commands of DS1000E 2.2.2]
* [http://www.rcgroups.com/forums/showpost.php?p=15479444&postcount=912 Some 2.4.0.3 undocumented 488 commands]
* [http://www.rigolna.com/pdfs/Programming_Guides/DS1000E_Programming_Guide.pdf DS1000E Programming Guide]

Hardware/References

2012-01-08T20:37:51Z

Matt:

A list of relevant information links on the Rigol hardware.

== CPU ==
* [http://www.analog.com/static/imported-files/processor_manuals/bf533_hwr_Rev3.4.pdf Blackfin Processor Hardware Reference]
* [http://www.analog.com/static/imported-files/processor_manuals/blackfin_pgr.ref.man.rev1.3.pdf Blackfin Processor Programming Reference]
* [http://www.analog.com/static/imported-files/application_notes/EE-240_Rev4.pdf EE-240: ADSP-BF533 Blackfin Booting Process]
* [http://www.analog.com/static/imported-files/data_sheets/ADSP-BF531_BF532_BF533.pdf ADSP-BF531/ADSP-BF532/ADSP-BF533 Datasheet]

Main Page

2012-01-08T20:29:37Z

Matt:

{{:Main Page/Welcome}}

{{col-begin}}
{{col-2}}
{{HeadingA|Toolchain}}
====Getting started====
* [[Build the Toolchain]]
* [[Patch your Firmware]]
* [[Start Development]]

{{col-2}}
{{HeadingB|Reverse Engineering}}
* [[General Information]]

====Software====
* [[Mapfile]]
* [[Flirt Signatures]]
* [[Firmware Upgrade]]

====Hardware====
* [[JTAG]]
* [[Schematics]]
* [[Hardware/Pictures]]
* [[Hardware/References]]

{{col-end}}

{{col-begin}}
{{col-2}}
{{HeadingA|Applications & Guides}}

====Applications====
====Tutorials====
====Ideas====
* [[Waterfall Plot for FFT]]
* [[Protocol Analyzer]]
* [[Software Defined Radio]]

{{col-2}}
{{HeadingB|Developers & Writers}}

* [[User:krater|krater (Andreas Schuler)]]
* [[user:A Helene|A Helene]]
* [[user:matt|Matt (Matthew Ellis)]]

{{col-end}}

{| border="1" class="wikitable" style="background-color:orange; width:100%;"
|-
|colspan="4" style="background-color:orange; text-align:center;"| [[Disclaimer]]
|}

__NOTOC____NOEDITSECTION__

User:Matt

2012-01-08T20:16:03Z

Matt:

== Matthew Ellis ==
[[File:Matt.jpg|200px|thumb|left|^that^ would be me, just without a face...]]
'''''Bio:'''''
Well to start with i should mention am a college student in the UK studying IT, I have a background in playing around with electronics since I first got near a screwdriver. That has still not changed and I can never refuse to void the warranty on new pieces of kit to see how it all works. I have skills in Programming (embedded and pc), Electronics design, Reverse engineering and 3D modelling among others. My goal for this project is to help research the internals of rigol scopes, hopefully finding some nice hacks and giving rigol some challenges along the way :)

If anyone needs to get in contact feel free send me a email at matthewellis1995@gmail.com

User:Matt

2012-01-08T19:58:38Z

Matt:

== Matthew Ellis ==
[[File:Matt.jpg]200px|thumb|left|alt text]]
'''''Bio:'''''I

File:Matt.jpg

2012-01-08T19:57:35Z

Matt: profile picture for the user Matt

profile picture for the user Matt

User:Matt

2012-01-08T19:51:43Z

Matt: Created page with "'''''Bio:'''''I I am college student in the UK with a passion for anything that clicks, beeps or looks cool. I love to play with cool stuff whether it is hardware like an arduino..."

'''''Bio:'''''I
I am college student in the UK with a passion for anything that clicks, beeps or looks cool.
I love to play with cool stuff whether it is hardware like an arduino or coding a website.